System and method for calibrating an adjustable delay time for a delay module

ABSTRACT

A timing calibration system for an adjustable delay time of a delay module for an electronic circuit is provided. The system includes a control delay module including at least one calibration delay module, the control delay module having a second delay time. The system also includes a timing module associated with the control delay module, a comparison module associated with the timing module and an adjustment module for the delay module. The timing module measures the second delay time, the comparison module compares the second delay time with a desired delay time and produces a comparison result and the adjustment module calibrates the adjustable delay time utilizing the comparison result.

FIELD OF THE INVENTION

[0001] The invention relates generally to a system and method forcalibrating an adjustable delay time for a delay module.

BACKGROUND OF THE INVENTION

[0002] An application specific integrated circuit (ASIC) is a customelectronic circuit implemented using VLSI technologies that is designedfor a specific application. The circuit of the ASIC is made afterdesigning a hardware circuit in software by inserting and connectingvarious standardized devices together. The devices include latches,multiplexers, counters and logic gates. The software converts thelogical connections to a circuit pattern which can be implemented withthe ASIC.

[0003] A delay module is available for use in the ASIC circuit toprovide a delay of a predetermined amount of time. Methods typicallyused to make this adjustment to a signal utilize a delay-locked loop(DLL) or a phase-locked loop (PLL).

[0004] A DLL consists of a delay module with an adjustable delay timeand control logic. The DLL samples an input clock and a feedback clockand determines the appropriate delay time to ensure the input clock andthe feedback clock are in phase. It calibrates the adjustable delay timeof the delay module accordingly. Once the input clock and the feedbackclock are in phase, the DLL locks this delay time into the delay module.

[0005] A PLL uses a voltage controlled oscillator whose output phase orfrequency locks onto and tracks the phase of the feedback signal. ThePLL detects any phase difference between the two signals and generates acorrection voltage that is applied to the oscillator to adjust itsphase. Some PLLs also allow the output clock to have a 1/N clock periodphase shift which provides the fixed time delay.

[0006] Use of either of these techniques has disadvantages. The delaytime of the DLL varies on the characteristics of the phase comparator.The phase comparator of a DLL would have a limited granularity and itsdelay time would vary according to variations between circuits on thewafer introduced during the manufacturing process of the wafer,operating voltage and operating temperature for the circuit. A PLL issensitive to signal variations which requires meticulous layout of itscontrol signals. This sensitivity usually imparts restrictions on theplacement of the PLL on the die. This may also limit the number of PLLsthat can be placed on the die. Additionally, both a PLL and a DLLrequire a continuous clock to operate effectively. Gaps or variations inthe frequency in the clock signal will cause a PLL or DLL to lose lock.

[0007] Many ASIC manufacturers provide in their component library aprogrammable delay module having an adjustable delay time as an elementfor an ASIC. Typically, the delay module has an input signal, an outputsignal and a means for configuring the length of the delay time for theinput signal to propagate to the output signal.

[0008] A number of factors will cause the delay module in the ASIC tohave a delay time in a certain range rather than the desired delay time.This range can be as much as +/−40% from the delay time desired of thedelay module. Factors that affect the delay time are variations betweencircuits on the wafer introduced during the manufacturing process of thewafer (process factors), operating voltage and operating temperature forthe ASIC circuit.

[0009] Generally, process factors cause the largest variation in delaytimes. This occurs because each delay module may have variations indeposition sizes for the transistors and interconnections that are usedto create the delay module. Increases in voltage and temperature duringoperation of the ASIC may also lengthen the delay time of the delaymodule.

[0010] There exists a need for a system which addresses the deficienciesof providing accurate times for a delay module for an ASIC.

SUMMARY OF THE INVENTION

[0011] In a first aspect of the invention, a timing calibration systemfor an adjustable delay time of a delay module for an electronic circuitis provided. The system includes a control delay module including atleast one calibration delay module, the control delay module having asecond delay time. The system also includes a timing module associatedwith the control delay module, a comparison module associated with thetiming module and an adjustment module for the delay module. The timingmodule measures the second delay time, the comparison module comparesthe second delay time with a desired delay time and produces acomparison result and the adjustment module calibrates the adjustabledelay time utilizing the comparison result.

[0012] The desired delay time may include a desired delay time range andif the comparison module determines that the second delay time is lessthan a lower bound of the desired delay time range, the adjustmentmodule increases the adjustable delay time of the delay module. Also, ifthe comparison module determines that the second delay time is more thanan upper bound of the desired delay time range, the adjustment moduledecreases the adjustable delay time of the delay module.

[0013] The comparison module may include a first comparison sub-module,the first comparison sub-module comparing the second delay time to alower bound of the desired delay time range to produce a firstcomparison result and a second comparison sub-module, the secondcomparison sub-module comparing the second delay time to an upper boundof the desired delay time range to produce a second comparison result,and the adjustment module includes a counter controlled by an enablementpulse, the counter reacting to the first and the second comparisonresult and the adjustment module calibrates the adjustable delay timebased on the counter.

[0014] The system may include a signal generator, the signal generatorgenerating a pulse signal provided as a first input signal to the timingmodule and a second input signal to the control delay module, thecontrol delay module producing an output signal provided as a thirdinput signal to the timing module.

[0015] The system may provide for an edge of the first input signalinitiating the timing module to start a timer and an edge of the thirdinput signal stoping the timer, the second delay time being an amount oftime measured by the timer.

[0016] The delay module may include at least one delay sub-module andthe calibration delay modules may include a number of calibration delaymodules.

[0017] The calibration delay modules may include a facsimile of thedelay module.

[0018] The adjustment module may calibrate the second delay time of thecontrol delay module.

[0019] The timing module may be a counter.

[0020] The comparison module may be a comparator.

[0021] The system may also include a desired delay time registerassociated with the comparison module, the desired delay time registerstoring the desired delay time and providing the desired delay time tothe comparison module. The system may also include an adjustmentregister associated with the adjustment module, the adjustment registerstoring an adjustment value generated by the adjustment module, theadjustment module adjusting the adjustable delay time of the delaymodule utilizing the adjustment value.

[0022] The system may also include a range lock for the desired delaytime register, the range lock selectively preventing alteration of thedesired delay time stored in the desired delay time register.

[0023] The system may also include an adjustment lock for the adjustmentregister, the adjustment lock selectively preventing alteration of theadjustment value stored in the adjustment register.

[0024] The system may also include a processor associated with theadjustment module, the processor operating a program which provides thedesired delay time to the desired delay time register, accesses anoutput from the adjustment module, generates the adjustment value fromthe output and provides the adjustment value to the adjustment register.

[0025] The system may be embodied in an ASIC.

[0026] In a second aspect of the invention, a calibrated delay modulefor an electronic circuit is provided. The module includes a delaymodule having an adjustable delay time, a control delay modulecomprising at least one calibration delay module, the control delaymodule having a second delay time, a timing module associated with thecontrol delay module, a comparison module associated with the timingmodule and an adjustment module for the delay module. The timing modulemeasures the second delay time, the comparison module compares thesecond delay time with a desired delay time and produces a comparisonresult and the adjustment module calibrates the adjustable delay timeutilizing the comparison result.

[0027] In a third aspect of the invention, a method of calibrating anadjustable delay time associated with a delay module for an electroniccircuit is provided. The method includes the steps of measuring acumulative delay time in a control delay module of the electroniccircuit, the cumulative delay time being a function of the adjustabledelay time, comparing the cumulative delay time with a desired delaytime to produce a comparison result and calibrating the adjustable delaytime of the delay module based on the comparison result.

[0028] In a fourth aspect of the invention, a calibration system for anadjustable unit value of a unit module for an electronic circuit isprovided. The system includes a control module comprising at least onescaled unit module, the control module having a scaled unit value, ameasurement module associated with the control module, a comparisonmodule associated with the measurement module and an adjustment modulefor the unit module. The measurement module measures the scaled unitvalue, the comparison module compares the scaled unit value with adesired unit value and produces a comparison result and the adjustmentmodule calibrates the adjustable unit value based on the comparisonresult.

[0029] In other aspects, the invention provides various combinations andsubsets of the aspects described above.

BRIEF DESCRIPTION OF THE DRAWINGS

[0030] The foregoing and other aspects of the invention will become moreapparent from the following description of specific embodiments thereofand the accompanying drawings which illustrate, by way of example only,the principles of the invention. In the drawings, where like elementsfeature like reference numerals (and wherein individual elements bearunique alphabetical suffixes):

[0031]FIG. 1 is a block diagram showing a calibration module for anelectronic circuit in accordance with an embodiment of the invention;

[0032]FIG. 2 is a timing diagram of the timing signals of thecalibration module of the electronic circuit of FIG. 1;

[0033]FIG. 3 is a block diagram of a register, comparison module andadjustment module of another embodiment of the calibration module;

[0034]FIG. 4 is a block diagram of a delay module of the electroniccircuit of FIG. 1;

[0035]FIG. 5 is a block diagram of a control delay module of theelectronic circuit of FIG. 1;

[0036]FIG. 6 is a block diagram of another embodiment of the calibrationmodule, shown in part, utilizing a CPU with an electronic circuit inaccordance with another embodiment of the invention;

[0037]FIG. 7 is a state diagram of state transitions of the electroniccircuit of FIG. 1; and,

[0038]FIG. 8 is a table of an example of delay times and count valuescalculated by the calibration module of FIG. 1.

DETAILED DESCRIPTION OF AN EMBODIMENT

[0039] The description which follows, and the embodiments describedtherein, are provided by way of illustration of an example, or examples,of particular embodiments of the principles of the present invention.These examples are provided for the purposes of explanation, and notlimitation, of those principles and of the invention. In the descriptionwhich follows, like parts are marked throughout the specification andthe drawings with the same respective reference numerals.

[0040] The embodiment relates to a system and method for calibrating anadjustable delay time of a delay module. The embodiment is suited foruse in an ASIC. However, it will be appreciated that the system may beused in other circuits, including discrete circuits.

[0041] Briefly, the system of the embodiment calibrates an adjustabledelay time for a delay module in the following manner. The system has acontrol delay module having a number of delay sub-elements. Eachsub-element is a facsimile if not a copy of the delay element. Thecontrol delay module generates a calibrated timing signal related to thedesired delay time for the delay module. In the embodiment, thecalibrated timing signal represents a cumulative delay time for thesub-elements which is related to the adjustable delay time of the delaymodule. The cumulative delay time can then be compared against a scaledvalue of the desired delay time for the delay module. From thecomparison, the delay module can be adjusted to produce a delay timecalibrated towards the desired delay time. This system and methodprovides a mechanism for providing a calibrated delay time for a delaymodule without using a PLL or a DLL. The system and method also do notrequire a signal to propagate through the delay module in order tocalibrate its adjustable delay time. Accordingly, the system and methodcan operate independently of the delay module. Additionally, unlike aPLL or DLL system having a localized calibration system, one system maycalibrate multiple delay modules.

[0042] First, referring to FIG. 1, a description of an electroniccircuit containing an embodiment of the system and method is provided.In a broad aspect, electronic circuit 100 has calibration module 101 anddelay module 128.

[0043] Delay module 128 provides a programmable delay time for an ASICby providing a stepped range of possible delay times for delay module128. The input signal 130 is provided to delay module 128 and is delayedby a programmable amount of time, Δ. Output signal 132 is produced bydelay module 128 and is a Δ-delayed version of signal 130. Δ is set byproviding suitable control signals 134 to control input 136 of delaymodule 128.

[0044] Calibration module 101 generates control signals 134. Calibrationmodule 101 comprises signal generator 102, control delay module 106,timing module 108, clock 110, comparison module 120, adjustment module122 and register 118. As is discussed below, various modules incalibration module 101 generate input and output signals which aremanipulated by other modules in calibration module 101 to ultimatelygenerate control signal 134.

[0045] To begin a calibration cycle, signal generator 102 generatespulse signal 104. Control delay module 106 receives pulse signal 104 andpropagates it through its internal delay elements. The pulse isultimately delayed by module 106 by a measurable amount of time. It isthe amount of time that pulse signal 104 is delayed by control delaymodule 106 which provides basic data on how to calibrate delay module128. Output signal 107 is a delayed version of pulse signal 104. Controldelay module 106 provides a stepped range of possible delay times. Itwill be appreciated that pulse signal 104 and clock signal 112 may bederived from the same signal generator.

[0046] Timing module 108 measures the delay time between pulse signal104 and output signal 107. Time measurement by timing module 108 isactivated by the leading edge of pulse signal 104 which is provided tostart terminal 140. Time measurement by timing module 108 is deactivatedby the leading edge of output signal 107 which is provided to stopterminal 144. A count value for the measured time is encoded in n-bit intiming module 108 on output lines 146. Clock 110 produces clock signal112 which is provided to the clock input 113 of timing module 108.Accordingly timing module 108 counts the number of pulses in clocksignal 112 from when the module is activated to when it is deactivated.

[0047] The count value is dependent on the difference in time betweenthe arrival of the leading edges of pulse signal 104 and output signal107 at timing module 108 and the frequency of clock signal 112. Thepropagation time of pulse signal 104 through control delay module 106 isthe value of the count value in timing module 108 multiplied by theclock period of clock signal 112.

[0048] Once the count value of the delay time for control module 106 ismeasured, the count value must be compared against a calibration valuerelated to a desired count value for the delay module 128. The desiredcount value is calculated from the desired delay time for control delaymodule 106 given the delay time required for electronic circuit 100.Comparison module 120 performs the comparison function. The count valuemeasured from control delay module 106 is provided to comparison module120 via output signals 146 to compare the count value against thiscalibration value. In the embodiment, this calibration value is a binaryvalue of a desired delay time of control delay module 106 divided by theclock period of clock signal 112. Comparison module 120 produces acomparison result which is sent to adjustment module 122 in controlsignal 150. Further detail on the operation of comparison module 120 isprovided later.

[0049] Adjustment module 122 adjusts the programmable delay time ofdelay module 128 based on the result provided by comparison module 120.Control delay module 106 is also re-calibrated. This is done throughcontrol signal 160 provided to control terminal 162 of control delaymodule 106. Afterwards, a new pulse signal 104 may be sent to by controldelay module 106 and delay module 128 may be calibrated again.

[0050] In the embodiment, timing module 108 is a timer, clock signal 112is a 334 MHz clock signal and comparison module 120 is a comparator.

[0051] Referring to FIG. 2, timing diagram 200 illustrates pulse signal104 provided to start terminal 140 at time 202 wherein, at that time,the counting is initiated. Output signal 107 generated from controlmodule 106 is delayed by delay 220 of Δ′ from the initiation of inputpulse 104. The rising edge of output signal 107 stops timing module 108at time 204.

[0052] Output signal 107 is also used to generate enablement pulsesignal 116 which is provided to enablement input 152 of adjustmentmodule 122 at time 206. Upon being activated by enablement pulse signal116, adjustment module 122 determines an adjustment value for delaymodule 128 based on the produced comparison result. The adjustment valueis stored in register 124 and provided as a binary signal 134 to controlinput 136 of delay module 128.

[0053] In the embodiment, adjustment module 122 determines whether thedelay should be increased, decreased or not adjusted. If adjustmentmodule 122 determines that the delay for delay module 128 should beadjusted, it sends control signal 134 which causes delay module 128 toincrease or decrease its adjustable delay time by one step. Controldelay module 106 is similarly adjusted by sending control signal 160. Ifthe delay for delay module 128 requires further adjustment, calibrationmodule 101 adjusts delay module 128 upon calibration module 101performing another calibration cycle beginning with another pulse signal104. It will be appreciated that calibration module 101 may beprogrammed to adjust the adjustable delay time of delay module 128 bymore than one step in a calibration cycle. This adjustment may initiallyover-compensate for the variation in the delay time of delay module 128from its desired delay time. Calibration module 101 then re-adjustsdelay module 128. Programming calibration module 101 with an adjustmentalgorithm which results in a series of over-compensating adjustmentsprovides an under-damped adjustment scheme for calibration module 101.Similarly, calibration module 101 may be programmed to calculate thenumber of steps to adjust the adjustable delay time of delay module 128providing a critically-damped adjustment scheme. The embodiment providesan over-damped adjustment scheme which does not over-compensate for thevariation in the delay time of delay module 128 but approaches itsdesired delay time in one step increments.

[0054] It will be appreciated that calibration of delay module 128 mayonly be accomplished in a window of time between time 204 and time 208.Calibration may not be accomplished prior to time 204 since the delaytime propagated to output signal 107 is not known before this time.Output signal 107 also generates clear pulse signal 114 which clearstiming module 108 at time 208 (FIG. 2). Calibration may not beaccomplished after time 208 since timing module 108 has been reset afterthis point. The relative timing of the transitions of the signalsproduces these boundaries. Calibration module 101 is implemented using astate machine to control the timing of signals.

[0055] Referring to FIG. 7, state diagram 700 illustrating the statesand transitions for the algorithm of calibration module 101 is shown.Calibration module 101 is at Reset state 702 on start up of the systememploying delay module 128. Calibration module 101 moves to Begin Clockstate 704 upon receipt of pulse signal 104 by timing module 108 to beginto measure the count value of control delay module 106. When outputsignal 107 reaches timing module 108 to complete the measurement of thecount value, calibration module 101 progresses to Stop Clock state 710.In this state, comparison module 120 produces a meaningful comparison ofthe count value associated with the delay time of control delay module106 and the count value associated with the desired delay time containedin register 118. Enablement pulse signal 116 moves calibration module101 into Adjust Delay state 714. The arrival of enablement pulse signal116 at adjustment module 122 enables calibration module 101 to makeadjustments after comparator 120 compares the count value measured fromcontrol delay module 106 with the count value in register 118.Accordingly, adjustment module 122 is prevented from modifying delaymodule 128 prior to receiving a meaningful comparison result fromcomparison module 120. Clear pulse signal 114 clears timing module 108which moves calibration module 101 back into Reset state 702.

[0056] It will be appreciated that, since control delay module 106 hasfinite granularity for the steps of its possible delay times, the scaleddesired delay time of control delay module 106 may not be equal to oneof the possible values for its delay time. As such, adjusting the delaytime of control delay module 106 will overshoot its scaled desired delaytime. For example, the delay time of control delay module 106 may be toolong resulting in a decrease in its delay time and the delay time ofdelay module 128. This one step decrease results in the delay time beingtoo short. The next calibration cycle will then increase the delay timeof control delay module 106 and the delay time of delay module 128 byone step resulting in a delay time which is again too long. Acalibration module employing this scheme may result in oscillating delaytimes for control delay module 106 and delay module 128. In anotherembodiment, this oscillation is avoided by using a scaled desired delaytime range for the scaled desired delay time. Accordingly, the delaytime generated by control delay module 106 does not require adjustmentof delay module 128 if the delay time is within the scaled desired delaytime range.

[0057] Referring to FIG. 3, another adjustment mechanism is shown whereregister 118 comprises maximum delay time register 302 for storing acount value associated with an upper bound of the desired delay timerange and minimum delay time register 304 for storing a count valueassociated with a lower bound of the desired delay time range. The countvalues associated with the upper and lower bounds are simultaneouslycompared with the count value associated with the delay time produced bycontrol delay module 106 in comparison module 120, the upper bound countvalue being compared with the delay time count value by comparisonsub-module 306 and the lower bound count value being compared with thedelay time count value by comparison sub-module 308. The results ofthese comparisons are sent to adjustment module 122. Two AND gates 310and 312 in adjustment module 122 separately receive each result fromcomparison sub-modules 306 and 308. Upon receiving enablement pulsesignal 116 at time 206, if the comparison indicates that the delay timeis below the desired delay time range, AND gate 312 will produce anoutput signal indicating that the delay time should be increased. If thecomparison indicates that the delay time is above the desired delay timerange, AND gate 310 will produce an output signal indicating that thedelay time should be decreased. It will be appreciated that at most oneof the comparisons will generate an adjustment condition. The increaseor decrease signal is provided to counter 320 at its respective countincrease and count decrease inputs to produce a control signal whichcauses adjustment module 122 to either increase or decrease the delaytime in delay element 128 by one step. It will also be appreciated thatneither AND gate 310 or AND gate 312 may produce signals indicating thatthe delay time should be increased. In this case, no signal is providedto counter 320 and delay elements 128 and 106 are not adjusted. As notedearlier, it will be appreciated that adjustment module 122 may beprovided with sufficient logic to produce an under-damped or acritically-damped delay module 128.

[0058] Referring to FIG. 4, delay module 128 comprises a plurality ofdelay sub-modules 406 connected in series from input terminal 420 tooutput terminal 422. Accordingly, a signal entering delay module 128will propagate through each element 406 as per arrow 412. In theembodiment, each delay sub-module 406 is an inverting multiplexer whichhas a nominal propagation delay of 80 ps and delay module 128 consistsof thirty-two (32) of such delay sub-modules 406(1), 406(2) . . .406(32). Delay module 128 also utilizes an alternating inverted andnon-inverted input signal 130 a and 130 b between successive delaysub-modules 406 thereby minimizing the duty-cycle distortion of thedelayed signal. This alternating pattern “averages out” propagationdiscrepancies between propagation delays related to low-to-high signaltransitions and high-to-low signal transitions in sub-modules 406. Itwill be appreciated that there may be any number of delay sub-modules406 in delay module 128 and delay sub-module 406 may be any componentthat can be configured to produce a defined delay time including ANDgates, OR gates, enabled latches, buffers and resistor-capacitor delays.

[0059] As described above, the embodiment allows for the adjustment ofthe delay time of delay module 128. This is accomplished by activating aselected number of sequential sub-modules 406 and propagating the signalthrough that block. Sub-modules 406 are individually activated by theirenable pins 430. As shown in FIG. 4, as there are 32 delay sub-modules406 in delay module 128, five binary control lines 408 (2⁵=32) arerequired to access each of enable pins 430 of the 32 delay sub-modules406. Accordingly, in the embodiment, adjustment module 122 issues afive-bit binary signal to decoder 402 through control lines 408 toactivate a selected block of delay sub-modules 406. Decoder 402activates the selected number of delay sub-modules 406 by sending aninput signal to enable pins 430 of selection devices 404 controllingtheir delay sub-modules 406. In the embodiment, selection devices 404are flip-flops controlled by external clock signal 410.

[0060] In the embodiment, adjustment module 122 responsively increasesor decreases the adjustable delay time of delay module 128 by activatingor deactivating an additional delay sub-module 406 from the number ofactivated sub-modules per calibration cycle, i.e. one iteration ofcalibration module 101 beginning with pulse signal 104. It will beappreciated that the increase or decrease in the adjustable delay timeof delay module 128 may be accomplished by activating or deactivatingmore than one delay sub-module 406 per calibration cycle. It will alsobe appreciated that adjustment module 122 need not gradually increasenor gradually decrease the adjustable delay time of delay module 128 butmay activate or deactivate the appropriate number of delay sub-modules406 in one calibration cycle.

[0061] Referring to FIG. 5, as described earlier, control delay module106 is adjusted to mimic adjustments made to delay module 128. In theembodiment, control delay module 106 contains N calibration delaymodules 502(1) to 502(N), each contributing to the delay time of controldelay module 106. In the embodiment, each calibration delay module 502is a facsimile of delay module 128 with a similar logical layout and thesame number of delay sub-modules 406. As such, by activating the samenumber of delay sub-modules 406 in delay module 128 as in each ofcalibration delay modules 502, a linear relationship between the delayintroduced by control delay module 106 and delay module 128 is produced.This one-to-one relationship provides a straightforward delaycalculation scheme for calibrating delay cell 128. To maintain thisrelationship for this scheme, adjustment module 122 provides controlsignal 160 to control delay module 106 at control terminal 162 toactivate the same number of active delay sub-modules 406 in eachcalibration delay module 502 as are active in delay module 128 aftercalibrating delay module 128. It will be appreciated that adjustment ofdelay module 128 may be delayed until the measured delay time of controldelay module 106 differs from the desired delay time by a certainpercentage. In this case, control delay module 106 is still updated ifthe measured delay time of control delay module 106 is more or less thanits desired delay time. Adjustment module 122 then adjusts delay module128 when the measured delay time of control delay module 106 differsfrom the desired delay time by the necessary percentage.

[0062] While the above configuration of control delay module 106provides a straightforward calculation scheme, it will be appreciatedthat control delay module 106 need not contain multiple calibrationdelay modules 502(1) to 502(N) but, in another embodiment, may containonly one calibration delay module 502. Further, it will also beappreciated that each calibration delay module 502 may have a differentnumber of delay sub-modules 406 than delay module 128. Any timingrelationship between control delay module 106, calibration delay modules502(1) to 502(N) and delay module 128 may be used to generate scalingfactors to adjust delay module 128. However, these alternative schemeswould require calculation mechanisms which consider such less directscaling relationships between the number of delay sub-modules 502 anddelay module 128 when calculating adjustments for delay module 128.

[0063] It will be appreciated that as the number of calibration delaymodules 502 of control delay module 106 increases, the results fromcalibration module 101 become more precise in calibrating the adjustabledelay time of delay module 128. It will also be appreciated that as theperiod of clock signal 112 decreases, the results from calibrationmodule 101 also become more precise in calibrating the adjustable delaytime of delay module 128. It will be appreciated that there is littlepractical benefit to providing a system having greater precision intiming than the smallest unit of measurement of the delay module 128being calibrated.

[0064] In the embodiment, there are 100 calibration delay modules 502(1)to 502(100) in control delay module 106. In the embodiment, register 118contains a programmed binary value which represents a count value of thedesired delay time of output signal 107 divided by the clock period ofclock signal 112. Because of the one-to-one relationship betweencalibration delay modules 502 and delay module 128, the binary value ofregister 118 represents a count value that is approximately equal to 100times the desired delay time of delay module 128 divided by the clockperiod of clock signal 112. It will be appreciated that the binary valueof register 118 may also represent a range of count values. It willfurther be appreciated that register 118 may have a representation of adifferent count representing the desired delay.

[0065] It will be appreciated that the binary value stored in register118 may represent the count value associated with the desired delay timeor range of delay module 128 rather than that of control delay module106. In such a case, calibration module 101 processes the count valuebefore comparing the desired delay time or range count value with themeasured delay time count value of control delay module 106 to accountfor additional delay time propagated in control delay module 106 apartfrom calibration delay modules 502. Calibration module 101 then eithermultiplies the binary value from register 118 by the number ofcalibration delay modules 502 in control delay module 106 or takes theaverage of the delay time propagated by each calibration delay modules502.

[0066] Referring to FIG. 8, values of delay times and count values isgiven in Table 800 for an example of the calculations of the embodimentof FIG. 1. The measured count value of control delay module 106 (column806) and its corresponding delay time (column 804) is shown for thenumber of delay sub-modules 406 active in each calibration delay module502 of control delay module 106 (column 802).

[0067] In the example, the desired delay time of delay module 128 is0.96 ns. Initially there are 12 delay sub-modules 406 active in delaymodule 128 to provide this 0.96 ns delay (12×80 ps). To maintain theone-to-one relationship of the embodiment, 12 delay sub-modules 406 arealso active in each of calibration delay modules 502(1) to 502(100) incontrol delay module 106. Assuming no delay is introduced by elementsother than calibration delay modules 502, the desired delay time ofcontrol delay module 106 is 96 ns (100×0.96 ns). The frequency of clocksignal 112 is 2 GHz resulting in a clock period of 0.5 ns/cycle.Accordingly, the binary value stored in register 118 represents a countvalue of 192 cycles (96 ns÷0.5 ns/cycle).

[0068] Calibration module 101 performs a calibration cycle. Pulse signal104 propagates through control delay module 106. Timing module 108measures this delay at a count value of 288 cycles or 144 ns. Assumingthat delay module 128 produces the average delay time of calibrationdelay modules 502, delay module 128 will be producing a delay time of1.44 ns, or a delay time 33% longer than desired. Comparison module 120produces control signal 150 which indicates that the delay time islonger than desired and adjustment module 122 reduces the number ofactive delay sub-modules 406 in delay module 128 to 11. To maintain theone-to-one relationship, calibration module 101 also reduces the numberof active delay sub-modules 406 in each calibration delay module 502 to11.

[0069] Another calibration cycle measures the delay time of controldelay module 106 at a count value of 264 cycles or 132 ns. Since thisexceeds the desired count value of 192 cycles, calibration module 101again reduces the number of active delay sub-modules 406 in delaymodule. Further calibration cycles continue reducing the number ofactive delay sub-modules 406 since, as shown by table 800, column 806,at 10 and 9 active delay sub-modules 406, the count value of controldelay module 106 exceeds the desired count value represented by thebinary value in register 118.

[0070] The fourth calibration cycle reduces the number of active delaysub-modules 406 to 8. A fifth calibration cycle measures the delay timeof control delay module at a count value of 192 cycles or 96 ns. Delaymodule 128 should therefore produce a delay time of 0.96 ns, the desireddelay time. Comparison module 120 produces a control signal 150 thatdoes not direct adjustment module 122 to adjust delay module 128.Accordingly, no adjustment is made. Additional calibration cycles areperformed periodically to account for any additional variation in thedelay time of delay module 128. A 2 GHz clock is used in the example forease of calculation rather than the 334 Mhz clock of the embodiment. Itwill be appreciated that the above example does not adhere to practicalprecision limitations described earlier.

[0071] Referring to FIG. 6, in another embodiment, CPU 602 controlsaspects of calibration module 101. Software operating on CPU 602controls values provided to register 118. Calibration module 101 alsohas threshold lock 604. Threshold lock 604 prevents the count associatedwith the desired delay time stored in register 118 from beinginadvertently updated by the software until threshold lock 604 isdeactivated. This ensures that the software on CPU 602 has a safeguardwhen updating count values of the desired delay time. In the embodiment,threshold lock 604 does not allow the values stored in register 118 tobe updated before adjustment module 122 receives enablement pulse 116 attime 206. After CPU updates register 118, threshold lock 604 re-locks.It will be appreciated that any method may be used to re-lock thresholdlock 604 after CPU updates register 118. For example, threshold lock 604may be set to re-lock after a certain period of time or threshold lock604 may be explicitly re-locked after CPU updates register 118.

[0072] In the embodiment, register 610 contains the value used to updatedelay module 128 rather than register 124. Additionally, calibrationmodule 101 has delay lock 606 associated with register 610. Delay lock606 prevents the updating of register 610 until delay lock 606 isdeactivated. Software on CPU 602 obtains the value to be stored inregister 610 from adjustment module 122 which determines how tocalibrate delay module 128. It then unlocks delay lock 606 and writesthe value to be stored in register 610. The software on CPU 602 thencontrols the sending of control signal 134 to input terminal 136 ofdelay module 128 to adjust its adjustable delay time. After CPU updatesregister 610, delay lock 606 re-locks. Again, it will be appreciatedthat any method may be used to re-lock delay lock 606 after CPU updatesregister 610.

[0073] It will be appreciated that one register may be used in place ofthe two registers 124 and 610; however, separating these registersallows for a different value to be stored in register 124 from register610. A single calibration module 101 may then adjust multiple delaymodules 128 with varying delay times, each delay module 128 having aseparate register 610 for its own delay time.

[0074] It will be appreciated that calibration module 101 need notemploy software on CPU 602 to control adjustment module 122 and toupdate register 118. Instead, the logic for such control may be hardwired as a circuit into adjustment module 122 as well as the value forregister 118.

[0075] It will be appreciated that calibration module 101 may bedirected to perform more frequent calibration cycles on start up of thesystem employing delay module 128 to provide an initial calibration forprocess factors using the under-damped method described previously.After compensating for process factors, calibration module 101 thenperforms less frequent calibration cycles to compensate for voltage andtemperature changes in the system employing delay module 128.

[0076] It will be appreciated that the embodiment may be used in anelectronic circuit to calibrate other parameters. In that case, acontrol unit module has at least one scaled unit module, each scaledunit module having the same structure as a unit module to be calibrated.The control unit module produces a measurable value, measured by ameasurement module. Each scaled unit module would contribute to themeasurable value which is processed to produce a scaled unit value. Acomparison module compares the scaled unit value to a desired value forthe unit module to be calibrated. The comparison result is used tocalibrate the unit module. The values that may be calibrated in thismanner include voltage, current, power, capacitance, inductance,resistance or any other quantifiable parameter.

[0077] It is noted that those skilled in the art will appreciate thatvarious modifications of detail may be made to the embodiments describedherein, which would come within the spirit and scope of the invention asdefined in the following claims.

We claim:
 1. A timing calibration system for an adjustable delay time ofa delay module for an electronic circuit, said system comprising: acontrol delay module comprising at least one calibration delay module,said control delay module having a second delay time; a timing moduleassociated with said control delay module; a comparison moduleassociated with said timing module; and an adjustment module for saiddelay module; wherein said timing module measures said second delaytime, said comparison module compares said second delay time with adesired delay time and produces a comparison result and said adjustmentmodule calibrates said adjustable delay time utilizing said comparisonresult.
 2. A timing calibration system as claimed in claim 1, wherein:said desired delay time comprises a desired delay time range; if saidcomparison module determines that said second delay time is less than alower bound of said desired delay time range, said adjustment moduleincreases said adjustable delay time of said delay module; and if saidcomparison module determines that said second delay time is more than anupper bound of said desired delay time range, said adjustment moduledecreases said adjustable delay time of said delay module.
 3. A timingcalibration system as claimed in claim 2, wherein said comparison modulecomprises a first comparison sub-module, said first comparisonsub-module comparing said second delay time to a lower bound of saiddesired delay time range to produce a first comparison result and asecond comparison sub-module, said second comparison sub-modulecomparing said second delay time to an upper bound of said desired delaytime range to produce a second comparison result, and said adjustmentmodule comprising a counter controlled by an enablement pulse, saidcounter reacting to said first and said second comparison result andsaid adjustment module calibrates said adjustable delay time based onsaid counter.
 4. A timing calibration system as claimed in claim 1,wherein: if said comparison result indicates that said second delay timeis less than said desired delay time, said adjustment module increasessaid adjustable delay time of said delay module; and if said comparisonresult indicates that said second delay time is more than said desireddelay time, said adjustment module decreases said adjustable delay timeof said delay module.
 5. A timing calibration system as claimed in claim4, said system further comprising a signal generator, said signalgenerator generating a pulse signal provided as a first input signal tosaid timing module and a second input signal to said control delaymodule, said control delay module producing an output signal provided asa third input signal to said timing module.
 6. A timing calibrationsystem as claimed in claim 5, wherein an edge of said first input signalinitiates said timing module to start a timer and an edge of said thirdinput signal stops said timer, said second delay time being an amount oftime measured by said timer.
 7. A timing calibration system as claimedin claim 1, wherein said delay module comprises at least one delaysub-module and said at least one calibration delay module comprises aplurality of calibration delay modules.
 8. A timing calibration systemas claimed in claim 7, wherein each of said plurality of calibrationdelay modules comprises a facsimile of said delay module.
 9. A timingcalibration system as claimed in claim 7, wherein said adjustment modulecalibrates said second delay time of said control delay module.
 10. Atiming calibration system as claimed in claim 1, wherein said timingmodule is a counter.
 11. A timing calibration system as claimed in claim1, wherein said comparison module is a comparator.
 12. A timingcalibration system as claimed in claim 1, further comprising: a desireddelay time register associated with said comparison module, said desireddelay time register storing said desired delay time and providing saiddesired delay time to said comparison module; and an adjustment registerassociated with said adjustment module, said adjustment register storingan adjustment value generated by said adjustment module, said adjustmentmodule adjusting said adjustable delay time of said delay moduleutilizing said adjustment value.
 13. A timing calibration system asclaimed in claim 12, further comprising a range lock for said desireddelay time register, said range lock selectively preventing alterationof said desired delay time stored in said desired delay time register.14. A timing calibration system as claimed in claim 13, furthercomprising an adjustment lock for said adjustment register, saidadjustment lock selectively preventing alteration of said adjustmentvalue stored in said adjustment register.
 15. A timing calibrationsystem as claimed in claim 14, further comprising a processor associatedwith said adjustment module, said processor operating a program whichprovides said desired delay time to said desired delay time register,accesses an output from said adjustment module, generates saidadjustment value from said output and provides said adjustment value tosaid adjustment register.
 16. A timing calibration system as claimed inclaim 14, wherein said timing calibration system is embodied in an ASIC.17. A calibrated delay module for an electronic circuit, said modulecomprising: a delay module having an adjustable delay time; a controldelay module comprising at least one calibration delay module, saidcontrol delay module having a second delay time; a timing moduleassociated with said control delay module; a comparison moduleassociated with said timing module; and an adjustment module for saiddelay module, said adjustment module associated with said control delaymodule; wherein said timing module measures said second delay time, saidcomparison module compares said second delay time with a desired delaytime and produces a comparison result and said adjustment modulecalibrates said adjustable delay time utilizing said comparison result.18. A calibrated delay module as claimed in claim 17, wherein: saiddesired delay time comprises a desired delay time range; if saidcomparison module determines that said second delay time is less than alower bound of said desired delay time range, said adjustment moduleincreases said adjustable delay time of said delay module; and if saidcomparison module determines that said second delay time is more than anupper bound of said desired delay time range, said adjustment moduledecreases said adjustable delay time of said delay module.
 19. Acalibrated delay module as claimed in claim 18, wherein said comparisonmodule comprises a first comparison sub-module, said first comparisonsub-module comparing said second delay time to a lower bound of saiddesired delay time range to produce a first comparison result and asecond comparison sub-module, said second comparison sub-modulecomparing said second delay time to an upper bound of said desired delaytime range to produce a second comparison result, and said adjustmentmodule comprising a counter controlled by an enablement pulse, saidcounter reacting to said first and said second comparison result andsaid adjustment module calibrates said adjustable delay time based onsaid counter.
 20. A calibrated delay module as claimed in claim 17,wherein: if said comparison result indicates that said second delay timeis less than said desired delay time, said adjustment module increasessaid adjustable delay time of said delay module; and if said comparisonresult indicates that said second delay time is more than said desireddelay time, said adjustment module decreases said adjustable delay timeof said delay module.
 21. A calibrated delay module as claimed in claim20, said system further comprising a signal generator, said signalgenerator generating a pulse signal provided as a first input signal tosaid timing module and a second input signal to said control delaymodule, said control delay module producing an output signal provided asa third input signal to said timing module.
 22. A calibrated delaymodule as claimed in claim 21, wherein an edge of said first inputsignal initiates said timing module to start a timer and an edge of saidthird input signal stops said timer, said second delay time being anamount of time measured by said timer.
 23. A calibrated delay module asclaimed in claim 17, wherein said delay module comprises at least onedelay sub-module and said at least one calibration delay modulecomprises a plurality of calibration delay modules.
 24. A calibrateddelay module as claimed in claim 23, wherein each of said plurality ofcalibration delay modules comprises a facsimile of said delay module.25. A calibrated delay module as claimed in claim 23, wherein saidadjustment module calibrates said second delay time of said controldelay module.
 26. A calibrated delay module as claimed in claim 17,wherein said timing module is a counter.
 27. A calibrated delay moduleas claimed in claim 17, wherein said comparison module is a comparator.28. A calibrated delay module as claimed in claim 17, furthercomprising: a desired delay time register associated with saidcomparison module, said desired delay time register storing said desireddelay time and providing said desired delay time to said comparisonmodule; and an adjustment register associated with said adjustmentmodule, said adjustment register storing an adjustment value generatedby said adjustment module, said adjustment module adjusting saidadjustable delay time of said delay module utilizing said adjustmentvalue.
 29. A calibrated delay module as claimed in claim 28, furthercomprising a range lock for said desired delay time register, said rangelock selectively preventing alteration of said desired delay time storedin said desired delay time register.
 30. A calibrated delay module asclaimed in claim 29, further comprising an adjustment lock for saidadjustment register, said adjustment lock selectively preventingalteration of said adjustment value stored in said adjustment register.31. A calibrated delay module as claimed in claim 30, further comprisinga processor associated with said adjustment module, said processoroperating a program which provides said desired delay time to saiddesired delay time register, accesses an output from said adjustmentmodule, generates said adjustment value from said output and providessaid adjustment value to said adjustment register.
 32. A calibrateddelay module as claimed in claim 30, wherein said timing calibrationsystem is embodied in an ASIC.
 33. A method of calibrating an adjustabledelay time associated with a delay module for an electronic circuit,said method comprising the steps of: measuring a cumulative delay timein a control delay module of said electronic circuit, said cumulativedelay time being a function of said adjustable delay time; comparingsaid cumulative delay time with a desired delay time to produce acomparison result; and calibrating said adjustable delay time of saiddelay module based on said comparison result.
 34. A method ofcalibrating an adjustable delay time as claimed in claim 33, wherein:said desired delay time comprises a desired delay time range; if saidcomparison result indicates that said second delay time is less than alower bound of said desired delay time range, said step of calibratingsaid adjustable delay time increases said adjustable delay time of saiddelay module; and if said comparison result indicates that said seconddelay time is more than an upper bound of said desired delay time range,said step of calibrating said adjustable delay time decreases saidadjustable delay time of said delay module.
 35. A method of calibratingan adjustable delay time as claimed in claim 34, wherein said comparisonresult comprises a first comparison result and a second comparisonresult and said step of comparing said cumulative delay time with adesired delay time compares said second delay time to a lower bound ofsaid desired delay time range to produce a said comparison result andcompares said second delay time to an upper bound of said desired delaytime range to produce said second comparison result and said step ofcalibrating said adjustable delay time calibrates said adjustable delaytime based on said first and said second comparison result.
 36. A methodof calibrating an adjustable delay time as claimed in claim 33, wherein:if said comparison result indicates that said second delay time is lessthan said desired delay time, said step of calibrating said adjustabledelay time increases said adjustable delay time of said delay module;and if said comparison result indicates that said second delay time ismore than said desired delay time, said step of calibrating saidadjustable delay time decreases said adjustable delay time of said delaymodule.
 37. A method of calibrating an adjustable delay time as claimedin claim 36, said method further comprising the step of generating apulse signal provided as a first input signal to said control delaymodule, and wherein said step of measuring said cumulative delay time insaid control delay module measures said cumulative delay time propagatedto said pulse signal.
 38. A method of calibrating an adjustable delaytime as claimed in claim 37, further comprising the step of calibratingsaid second delay time of said control delay module based on saidcomparison result.
 39. A calibration system for an adjustable unit valueof a unit module for an electronic circuit, said system comprising: acontrol module comprising at least one scaled unit module, said controlmodule having a scaled unit value; a measurement module associated withsaid control module; a comparison module associated with saidmeasurement module; and an adjustment module for said unit module;wherein said measurement module measures said scaled unit value, saidcomparison module compares said scaled unit value with a desired unitvalue and produces a comparison result and said adjustment modulecalibrates said adjustable unit value based on said comparison result.